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IS23SC1604
16-KBIT SECURED SERIAL EEPROM
FEATURES
* 16K serial EEPROM with security features * Comply with ISO/IEC Standard 7816-3 Synchronous Protocol * Store and validate security codes * Four protected application zones * Provide transport code security * Single 5V power supply for read/write/erase operations * Low power operation: -- 15 A (max.) standby current -- 3 mA (max.) read current at 300 KHz -- 4 mA (max.) write/erase current * 2 ms read access time at 300 KHz; 5 ms write cycle time * 300 KHz serial clock rate * High ESD protection: > 4 KV * High reliability: -- 1,000,000 erase/write cycles -- 10 years data retention * Standard CMOS Process * Wide operating temperature range -- 0C to +70C Commercial; -40C to +85C Industrial * Data access only after validation of security code * Permanent invalidation of device upon eight consecutive failed attempts to enter the correct security code * Separate read/write/erase access protections for each application zone * Allow the memory chip to be personalized if the internal security fuse is not blown. If the internal security fuse is blown, maximum security protection of the memory will always be enabled.
ISSI
DESCRIPTION
(R)
ADVANCE INFORMATION APRIL 2003
IS23SC1604 is a low-cost, low-power, highly secured 16K bits (2K x 8) serial EEPROM. It is fabricated using ISSI's advanced CMOS technology. The security features of IS23SC1604 provide high levels of memory security protection for smart card applications. The memory is partitioned into four application zones. Each individual application zone is protected by multiple security codes from unauthorized read/write/erase access to the zone. In addition, an internal security fuse is available for the card issuer to fully personalize the device before releasing it to customer. The device also features an internal high-voltage charge pump for memory programming, 1,000,000 write/erase cycles and ten years of data retention.
Pin Configuration: 8-pin Plastic DIP
Vcc RST CLK FUS
C1 C2 C3 C4
C5 C6 C7 C8
GND NC I/O PGM
Copyright (c) 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION Rev. 00E 04/10/03
1
IS23SC1604
Block Diagram
ISSI
POWER ON RESET HIGHVOLTAGE GENERATOR
(R)
Vcc GND
2007 x 8 EEPROM
RST PGM CLK
ADDRESS DECODER
FUS
SECURITY LOGIC
I/O
(open drain)
(internal pull-downs on CLK, FUS, and PGM and internal pull-up on RST)
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ADVANCE INFORMATION Rev. 00E 04/10/03
IS23SC1604
PIN NAMES(1)
ISO C1 C2 C3 C4 C5 C6 C7 C8 PAD 8 7 6 5 4 3 2 1 PAD Name Vcc RST CLK FUS GND NC I/O PGM Description Supply Voltage Reset
ISSI
(R)
Serial Clock and Address Control Security Fuse Pad Ground No Connect Bi-directional Data Programming Control
Note: 1. Pins CLK, FUS, and PGM have internal pull-downs. Pin RST has an internal pull-up.
PIN DESCRIPTIONS
Symbol Vcc RST Card Contact C1 C2 Name and Function Supply Voltage Reset: The device's RST pin can be used to clear the internal address counter. When CLK is LOW, a HIGH-to-LOW transition on RST resets the address counter to zero, and the first bit of memory will be output on I/O after the falling edge of RST. Also, the RST pin can be used to place the device in low power standby mode by placing RST in HIGH logic state and both PGM and FUS in LOW logic state. While RST is HIGH, the internal address counter will not be incremented with CLK. Serial Clock and Address Control: This is the device data clock pin. It is used to clock data bits into and out of the device. It also increments the internal address counter. Security Fuse Pad: This pin is used by card issuer to personalize the device before releasing it to the customer. When FUS pin is driven to logic HIGH state and the state of the internal security fuse is HIGH (not blown), the issuer can personalize the entire content of the memory with successful Security Code (SC) validation. When FUS pin is driven to logic LOW state and the state of the internal security fuse is HIGH (not blown), the full protection of the memory is enabled and the security features of the device can be tested by the issuer. After the device personalization is completed, the issuer should blow the internal security fuse to logic LOW state so that the full protection of the memory will always be enabled regardless of the state on FUS pin. (Refer to IS23SC1604 Security Levels and also Blowing Internal Security Fuse.) Ground No Connect Serial Data Input and Output: This pin is where the data bit is shifted in and out of the device when a clock pulse is applied to CLK pin. Programming Control: This pin is asserted HIGH to initiate memory write or erase operation.
CLK
C3
FUS
C4
GND NC I/O PGM
C5 C6 C7 C8
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ADVANCE INFORMATION Rev. 00E 04/10/03
3
IS23SC1604
IS23SC1604 OPERATIONS Power-On Reset (POR)
When the supply voltage is first applied to the device, the device initiates POR. All the internal flags are clear (refer to Definition of IS23SC1604 Internal Flags), and the internal address counter is reset to zero.
ISSI
(R)
Reset
With CLK LOW, a HIGH-to-LOW transition at RST resets the address counter to zero. After the falling edge of RST, the device outputs the first bit of the memory on I/O pin. The reset operation will have no effect on any internal flags (see AC Test Load).
The compare operation latches the user's input Security/ Erase Key bit into the device at the rising edge of CLK and the bit comparison is performed on the next falling edge of CLK. The compare and read operations are executed in the same manner. The device distinguishes between the two operations by testing the address counter for security/erase key code location and the state of corresponding security/erase key code valid comparison flag (see Read Timing Diagram).
Write
If write access to a memory bit is enabled, the content of the bit can be written over with a `0' value by performing the following sequence: select PGM (logic HIGH state), input `0' on the I/O pin, change CLK from LOWto-HIGH, deselect PGM (logic LOW state), wait for 5 ms programming delay, and then bring CLK down from HIGH-to-LOW to complete the write operation. The new state of the bit will be output at the end of the write operation after the falling edge of CLK for data verification (see Compare Timing Diagram).
Addressing
Addressing is handled by an internal address counter which is incremented on the falling edge of CLK. When the counter continues to increment past 16383, the counter will roll over back to zero. The counter can also be cleared to zero by the reset operation.
Read
If read access to a memory bit is enabled, the state of the bit can be read out of the device by incrementing the address counter to the bit location. The device outputs the state of the read bit on the I/O pin after the falling edge of the last clock pulse that increments the address counter to the read bit location. However, if the read access to the memory bit is inhibited, the state of the data bit will not be output and the I/O pin will be placed in high-impedance state `1' (see Reset Timing Diagram).
Erase
If erase access to a memory bit is enabled, the content of the bit can be written over with a `1' value with the erase operation. Although erase is performed on single bits, the erase operation writes FFH to the whole byte which contains the erased bits because the memory is organized into 8-bit bytes. The erase operation can be executed by performing the following sequence: select PGM (logic HIGH state), input `1' on the I/O pin, change CLK from LOW-to-HIGH, deselect PGM (logic LOW state), wait for 5 msec programming delay, and then bring CLK down from HIGH-to-LOW to complete the erase operation. The new state of the bit will be output at the end of the erase operation after the falling edge of CLK for data verification (see Compare Timing Diagram).
Compare
Compare operation allows users to input the security/ erase key code for the security/erase key code validation for read/write/erase access to protected application zones (refer to Security/Erase Key Code Validation Operation).
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IS23SC1604
Device Operations (1)
Operation Reset FUS X PGM X RST CLK 0 Description
ISSI
(R)
The address counter is reset to zero and the first bit of the memory is output after the falling edge of RST. The address counter is incremented and the first bit is output after the falling edge of the clock if read access to the bit location is enabled. Compare the input bit with the internal bit of the memory (for Security/Erase Key codes validation). The address counter is incremented on the falling edge of CLK. The input bit is latched into the device at the rising edge of CLK and the bit comparison is done on the next falling edge of CLK. For write operation (write a `0' to the current address), a `0' is placed on I/O before the rising edge of CLK. For erase byte operation (write FFH to the byte that contains the current bit), a `1' is placed on I/O before the rising edge of CLK. CLK must stay HIGH for 5 ms during memory programming. The new content of the current address will be output after the falling edge of CLK for verification.
INC/Read
X
0
0
INC/CMP
X
0
0
Erase/Write
X
1
0
Verify Standby
X 0
0 0
0 1 X
The device is placed into standby mode. In this mode, the address counter will not be incremented with clock pulse when RST is HIGH.
Note: 1. X = Don't Care.
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ADVANCE INFORMATION Rev. 00E 04/10/03
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IS23SC1604
ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(1)
Symbol Vcc VI / VO TSTG PMAX Parameter Supply Voltage Input/Output Voltage Storage Temperature Power Dissipation Min. -0.3 -0.3 -40 -- Max. 6 6 125 60
ISSI
Unit V V C mV
(R)
Note: 1. Stress greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
Operating Range
Range Commercial Industrial Ambient Temperature 0 to +70C -40 to +85C Vcc 5V 5V
Capacitance (1,2)
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 5 8 Unit pF pF
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, Vcc = 5.0V + 10%; GND = 0V, f = 1 MHz.
DC Electrical Characteristics(1) (TA = 0C to 70C, Vcc = 5.0 + 10%, GND = 0V )
Symbol Vcc ICC ICCP ICCSB VIL VIH VOL ILI ILH Parameter Supply Voltage Supply Read/Compare Current Supply Write/Erase Current Standby Supply Current Input Low Level Input High Level Output Low Level Input Leakage Current I/O Leakage Current VOH = 5V Open Drain IOL = 1 mA Test Conditions 4.5 TA = 25C, FCLK = 300 KHz TA = 25C Min. 5.0 -- -- Typ. 5.5 -- -- Max. V 3.0 4.0 15.0 0.8 Vcc + 0.3 0.4 50 50 mA mA A V V V A A Unit
TA = 25C, -- -- RST = 5V; FUS, CLK, PGM = 0V, IIO = 0 mA -0.3 2.0 -- -- -- -- -- -- -- --
Note: 1. There is a internal pull-up on pin RST. There are internal pull-downs on pins FUS, CLK, and PGM
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ADVANCE INFORMATION Rev. 00E 04/10/03
IS23SC1604
AC Test Conditions
Parameter Input Pulse Levels Input Rise and Fall Time Input and Output Timing and Reference Level Output Load Value GND to 3.0V 5 ns 0.8V and 2.0V 100 pF
ISSI
(R)
AC Test Load
GND Chip
4.7K
Test Point I/O 100 pF
AC Electrical Characteristics (TA = 0 to 70C, Vcc = 5.0V + 10%; GND = 0V)
Symbol fCLK tCLK tRH tDVR tCH tCL tDV tOH tSC tHC tCHP tDS tDH tSPR tHPR Parameter Clock Frequency Clock Cycle Time RST Hold Time Data Valid Reset to Address 0 CLK Pulse Width (High) CLK Pulse Width (Low) Data Access Data Hold Data in Setup (CMP Instruction) Data in Hold (CMP Instruction) CLK Pulse Width (High in Erase/Write) Data in Setup Data in Hold PGM Setup PGM Hold Min. -- 3.3 0.1 -- 0.2 0.2 -- 0 0 0.2 5.0 0.2 0 2.2 0.2 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 300 -- -- 2.0 -- -- 2.0 -- -- -- -- -- -- -- -- Unit KHz ms ms ms ms ms ms ms ms ms ms ms ms ms ms 7
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ADVANCE INFORMATION Rev. 00E 04/10/03
IS23SC1604
Reset Timing Diagram
ISSI
(R)
Address
Address = 0
CLK tRH
RST tDVR I/O Output Data Valid
Read Timing Diagram
Address tCLK CLK tDV tOH I/O
Ax
Ax + 1
tOH Output Data Valid
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ADVANCE INFORMATION Rev. 00E 04/10/03
IS23SC1604
Compare Timing Diagram
ISSI
(R)
Address
Ax
CLK tSC tHC tHC Input Data Valid
I/O
Input Data Valid
Data is latched into the device on the rising edge of CLK.
The bit compare is performed on the falling edge of CLK.
Write/Erase Timing Diagram
Read Address Ax
Program Ax tCHP
Verify Ax+1
CLK tSPR PGM tOH tDV tOH
Out Valid Data
tHPR tDV tDH tDS
Input Data Valid Out Valid Data
tDH
I/O
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IS23SC1604
IS23SC1604 MEMORY MAP
IS23SC1604 memory is divided into four Application Zones. Each Application Zone has a corresponding access security code, access attempts counter (only Application
ISSI
(R)
Zone 1), erase key, erase attempts counter, and data storage area. Below is the memory map table for IS23SC1604:
Memory Map
Symbol FZ IZ SC SCAC CPZ Application 1 SC1 S1AC EZ1 E1AC AZ1 Application 2 SC2 EZ2 E2AC AZ2 Application 3 SC3 EZ3 E3AC AZ3 Application 4 SC4 EZ4 E4AC AZ4 MTZ Application Zone 4 Security Code 13952 Application Zone 4 Erase Key Application Zone 4 EZ4 Attempts Counter Application Zone 4 Memory Test Zone 13968 13984 13992 16040 13967 13983 13991 16039 16055 16 16 8 16 16056 16288 16303 16383 1744 1746 1748 2005 1745 1747 1748 2004 2006 2 2 1 256 2 2007 Application Zone 3 Security Code 11864 Application Zone 3 Erase Key Application Zone 3 EZ3 Attempts Counter Application Zone 3 11880 11896 11904 11879 11895 11903 13951 16 16 8 1483 1485 1487 1484 1486 1487 1743 2 2 1 256 Application Zone 2 Security Code Application Zone 2 Erase Key Application Zone 2 EZ2 Attempts Counter Application Zone 2 9776 9792 9808 9816 9791 9807 9815 11863 16 16 8 1222 1224 1226 1223 1225 1226 1482 2 2 1 256 Application Zone 1 Security Code Application Zone 1 SC1 Attempts Counter Application Zone 1 Erase Key Application Zone 1 EZ1 Attempts Counter Application Zone 1 168 184 192 208 216 183 191 207 215 9775 16 8 16 8 9560 21 23 24 26 27 22 23 25 26 1221 2 1 2 1 1195 Description Fabrication Zone Issuer Zone Security Code Security Code Attempts Counter Code Protected Zone Start Bit Address 0 16 80 96 104 End Bit Address 15 79 95 103 167 Start ByteEnd Byte Bits AddressAddress 16 64 16 8 64 0 2 10 12 13 1 9 11 12 20 Bytes 2 8 2 1 8
2048 1227
2048 1488
2048 1749
Total Addressable EEPROM Memory Fuse Internal Security Fuse Last Bit Address
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IS23SC1604
IS23SC1604 MEMORY PARTITIONS Fabrication Zone (FZ)
This zone is programmed by the manufacturer. After the zone is programmed, the manufacturer disables the write/ erase access to this zone so that it cannot be changed by card issuer or card user.
ISSI
(R)
Application Zone Erase Keys Attempts Counter (E1AC, E2AC, E3AC, E4AC)
Counts number of failed attempts to input the correct application zone erase key to the device. After eight consecutive failed attempts, the erasure of the corresponding application zone will never be allowed (refer to Memory Access Table).
Issuer Zone (IZ)
This zone can only be programmed by the issuer during device personalization process.
Application Zones (AZ1, AZ2, AZ3, AZ4)
Each application zone provides protected data storage space for user application. The read, write and erase access to the application zone are controlled by the first two bits of the zone as well as the corresponding application zone security code and application zone erase key and the Security Code (refer to Memory Access Table). Memory Test Zone (MTZ) There are no protections on this zone.
Security Code (SC)
This code serves as master security password to access to device's memory. A special transport code is programmed into SC location by the manufacturer and it is only made known to the issuer. This special code secures the transport of the device between the manufacturer and the issuer. After the issuer successfully validates the transport code, SC can be freely altered as wished. After the internal security fuse is blown, SC protects the access to the four application zones of the device.
IS23SC1604 SECURITY LEVELS
There are two security levels available in IS23SC1604 which are controlled by the internal security fuse state and FUS pin. At security level 1, the issuer has access to the entire memory with successful Security Code (SC) validation and the issuer is allowed to personalize the content of the entire memory except the Fabrication Zone (FZ). At security level 2, the memory is fully protected by various security codes in the memory. When the card has been personalized, the internal security fuse should be blown to protect the card memory from unauthorized usage before the card is released to the customer (Refer to Blowing Internal Security Fuse ). Once the security fuse is blown, it cannot be changed again. Below is the truth table that shows how the security level can be set with the state of FUS input pin.
Security Code Attempts Counter (SCAC)
Counts number of failed attempts to input the correct Security Code (SC) to the device. After eight consecutive failed attempts, the device will be locked permanently.
Code Protected Zone (CPZ)
This zone is read access only. Access to erase or write to this zone is protected by Security Code (SC). Application Zone Security Codes (SC1, SC2, SC3, SC4) These codes protect access to individual application zones of the memory.
Application Zone Security Code Attempts Counter (S1AC)
Counts number of failed attempts to input the correct Application Zone 1 Security Code to the device. After eight consecutive failed attempts, the Application Zone 1 will be locked permanently.
Security Levels
FUS pin GND Vcc Vcc State of the Internal FUSE Don't Care HIGH (FUSE not blown) LOW (FUSE blown) Security Level 2 1 2
Application Zone Erase Keys (EZ1, EZ2, EZ3, EZ4)
These keys protect individual application zones (AZ1, AZ2, AZ3, AZ4) from unauthorized attempt to erase the zone.
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11
IS23SC1604
IS23SC1604 INTERNAL FLAGS
The IS23SC1604's internal flags enable/disable the read, write, and erase access to application zones (Refer to Memory Access Table). All the flags are clear upon power-on reset (POR). The flags can be set to logic `1' state by validating the corresponding security code through the validation process. Once the flag is enabled (`1' state), it cannot be cleared by any operations except POR. Security Code Valid Comparison Flag (SV) This flag is set to `1' after the Security Code (SC) is validated (see Security/Erase Key Code Validation). This flag protects an unpersonalized card from unauthorized usage. If the card has already been personalized, this flag provides master protection for the application zones (refer to Memory Access Table). Application Zone 1 Security Code Valid Comparison Flag (S1) This flag is set to `1' after the Application Zone 1 Security Code (SC1) is validated (see Security/Erase Key Code Validation). This flag provides access protection for Application Zone 1 (refer to Memory Access Table). Application Zone `m' Security Code Valid Comparison Flag (Sm) where `m' = 2, 3 or 4. This flag is set to `1' after the Application Zone `m' Security Code is validated (see Security/Erase Key Code Validation). This flag provides access protection for Application Zone `m' (refer to Memory Access Table).
ISSI
Application Zone `n' Erase Key Valid Comparison Flag (Sn) where `n' = 1, 2, 3 or 4.
(R)
This flag is set to `1' after the Application Zone `n' Erase Key is validated (see Write/Erase Timing Diagram). This flag provides protection for Application Zone `n' from unauthorized erasure of the zone (refer to Memory Access Table). Application Zone `n' write flag (Pn) where `n' = 1, 2, 3 or 4. This flag is set to `1' if the first bit of Application Zone `n' is `1' (Bit address: 216 for zone 1, 9816 for zone 2, 11904 for zone 3, or 13992 for zone 4). This flag enables write access to the corresponding application zone (refer to Memory Access Table). Application Zone `n' read flag (Rn) where `n' = 1, 2, 3 or 4. This flag is set to `1' when the second bit of Application Zone `n' is `1' (Bit address: 217 for zone 1, 9817 for zone 2, 11905 for zone 3, or 13993 for zone 4). This flag enables read access to the corresponding application zone (refer to Memory Access Table).
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IS23SC1604
Security/Erase Key Code Validation
ISSI
B. Read C. Compare D. Read E. Write F. Verify G. Erase
(R)
Operation
A. Reset
H. I. Verify Read
Address
0
1
2
RST
TCHP
TCHP
CLK
PGM
I/O
(mode)
0 Out Out Out Out In In In In
0
0
Out Out Out
1 Out
0 In
0 Out
1 In
1 Out
Out
Out
Security/Erase Code Flag
FZ, IZ, E
Security/Erase Code Zone (16-bits)
Security/Erase Code Attempts Counter
SECURITY/ERASE KEY CODE VALIDATION OPERATION (For SC, SC1, EZ1, EZ2, EZ3, and EZ4 validation)
A. Reset the address counter to zero. B. Send required number of clock pulses to increment the address counter to security/erase key code location. C. Input the security/erase key code bit by bit for code validation. D. After security/erase key code entry, look for the first logic `1' bit in security/erase key code attempts counter. If the `1' bit is found, do not increment the address. E. Write a `0' over the `1' bit in security/erase key code attempts counter at the current bit location. F. The chip outputs a `0' after programming is done. G. If the security/erase key code validation was successful, the corresponding comparison flag will be set to `1' on the rising edge of PGM and the security/erase key code attempts counter should be erased to reactivate the eight allowable attempts. (The validation operation can be aborted by setting CLK HIGH when PGM is still LOW.) H. If the comparison flag were successfully set to `1', the erasure of the attempt counter would be allowed and the device would output a `1' on I/O after the erase operation. Otherwise, the erasure of the attempt counter would be blocked and a `0' would be output on I/O. (The content of the attempt counter remains unchanged.) I. On the following edge of the clock, the address counter is incremented and the state of the next bit is output on I/O.
Notes: 1. The address counter does not increment from steps E to H. 2. After eight consecutive failed attempts to validate the security/erase key code, the corresponding flag will be locked at `0' permanently.
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IS23SC1604
Application Zone Security Code Validation
ISSI
Operation A. Reset B. Read C. and D. Compare E. Read
(R)
Address
0
1
2
RST
CLK
I/O
(mode)
Out
Out
Out
Out
In
In
In
In
In
Out
Security/Erase Code Flag
FZ, IZ, E
Security/Erase Code Zone (16-bits)
APPLICATION ZONE SECURITY CODE VALIDATION OPERATION (For SC2, SC3, and SC4 validation)
A. Reset the address counter to zero. B. Send required number of clock pulses to increment the address counter to application zone security code location. C. Input the application zone security code bit by bit for code validation. D. If the security code validation were successful, the corresponding comparison flag would be set to `1'. E. On the following edge of the clock, the address counter is incremented and the state of the next bit is output on I/O.
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IS23SC1604
Blowing Internal Security Fuse
ISSI
Operation Reset A. Read B. and C. Write D. Verify
(R)
Address
0
1
2
16288
0
RST
TCHP
CLK PGM I/O
(mode)
Out
Out
Out
Out
1 Out
0 In
0 Out
Out
Internal Fuse State
FZ, IZ, E
Internal Fuse
BLOWING INTERNAL SECURITY FUSE
A. Set the address counter between 16288 and 16303. B. Set FUS pin at Vcc or GND; set RST pin at Vcc. C. Write `0' to the current bit location. D. The chip outputs a `0' after programming is done. The state of the internal security fuse is now `0' (blown state).
Note: 1. SV flag must be enabled (HIGH state) to blow the internal security fuse.
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IS23SC1604
MEMORY ACCESS TABLE Security Level One
ISSI
(R)
At security level one (security fuse not blown and FUS pad at Vcc), the memory access is controlled by Security Code Valid Comparison Flag (SV) and Application Zone `n' read flag (Rn). Memory Access Conditions At Security Level 1 (Device Personalization) Erase (Write `1') No No Yes No Yes No Yes No Yes No Yes No Yes No Yes No Yes No No Yes Yes Write (Write `0') No No Yes No Yes Yes Yes No Yes No Yes No Yes No Yes No Yes No No Yes Yes
Fields FZ IZ SC SCAC CPZ SCn S1AC EZn EnAC AZn
SV X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 X
Rn X X X X X X X X X X X X X X X X X 0 1 X X
Read Yes Yes Yes No Yes Yes Yes Yes Yes No Yes Yes Yes No Yes Yes Yes No Yes Yes Yes
Compare No No No Yes No No No No No No No No No No No No No No No No No
MTZ
Note: 1. `n' corresponds to Application Zone `n' where `n' = 1, 2, 3, or 4.
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IS23SC1604
MEMORY ACCESS TABLE Security Level Two
ISSI
(R)
At security level two (security fuse blown or FUS pad at GND), memory access is controlled by SV, Sn, Pn, Rn and En flags. Memory Access Conditions At Security Level 2 (Product Release) Fields FZ IZ SC SCAC CPZ SCn SV X X 0 1 0 1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 1 X X 1 1 1 1 X Sn X X X X X X X X X 0 1 X 0 1 X 0 1 1 X 0 1 1 0 0 1 1 1 1 X Pn X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 1 X Rn X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X En X X X X X X X X X X X X X X X 0 0 1 X 0 0 1 X X 0 1 0 1 X Read Yes Yes No No Yes Yes Yes Yes No No No Yes Yes Yes No No No No Yes Yes Yes Yes No Yes Yes Yes Yes Yes Yes Erase Write (Write `1') (Write `0') Compare No No No Yes No Yes No Yes No No Yes No No Yes No No No Yes No No No Yes No No No Yes No Yes Yes No No No Yes Yes Yes No Yes No No Yes No Yes Yes No No No Yes No No Yes Yes No No No No Yes Yes Yes No No Yes No No No No No No Yes No No No No No No Yes No No No No No No No No No No No No
S1AC
EZn
EnAC
AZn
MTZ
Note: 1. `n' corresponds to Application Zone `n' where `n' = 1, 2, 3, or 4.
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IS23SC1604
ORDERING INFORMATION Commercial Range: 0C to +70C
Order Part Number IS23SC1604-X2 IS23SC1604-X3 IS23SC1604-X4 IS23SC1604-X5 IS23SC1604-X6 IS23SC1604-X7 IS23SC1604-X8 IS23SC1604-P Package Sorted wafer Dice in waffle pack after backgrinding to 8-9 mil. Dice in waffle pack after backgrinding to 10-11 mil. Sorted wafers on a ring Individual modules Taped modules Blank Cards 300-mil Plastic DIP
ISSI
(R)
Industrial Range: -40C to +85C
Order Part Number IS23SC1604-X2I IS23SC1604-X3I IS23SC1604-X4I IS23SC1604-X5I IS23SC1604-X6I IS23SC1604-X7I IS23SC1604-PI Package Sorted wafer Dice in waffle pack after backgrinding to 8-9 mil. Dice in waffle pack after backgrinding to 10-11 mil. Sorted wafers on a ring Individual modules Taped modules 300-mil Plastic DIP
ISSI
(R)
Integrated Silicon Solution, Inc.
2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com
18
Integrated Silicon Solution, Inc. -- 1-800-379-4774
ADVANCE INFORMATION Rev. 00E 04/10/03

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